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precision integrated analog front end, controller, and pwm for battery test and formation systems data sheet AD8452 rev. 0 document feedback information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 ?2017 analog devices, inc. all rights reserved. technical support www.analog.com features cc and cv battery test and formation modes with transparent and automatic switchover, for systems of 20 ah or less precise measurement of voltage and current independent feedback control blocks highly accurate, factory trimmed instrumentation and differential amplifiers in-amp for current sense gain: 66 v/v difference amplifier for voltage sense gain: 0.4 v/v stable over temperature: offset voltage drift <0.6 v/c (maximum) gain drift: <3 ppm/c (maximum) current sense cmrr: 120 db minimum popular smps control for charge/discharge high pwm linearity with internal ramp voltage 50 khz to 300 khz user controlled switching frequency synchronization output or input with adjustable phase shift programmable soft start applications battery formation and testing high efficiency battery test systems with recycle capability battery conditioning (charging and discharging) systems general description the AD8452 combines a precision analog front-end controller and switch mode power supply (smps), pulse-width modulator (pwm) driver into a single silicon platform for high volume battery testing and formation manufacturing. a precision instrumentation amplifier (in-amp) measures the battery charge/ discharge current to better than 0.1% accuracy, while an equally accurate difference amplifier measures the battery voltage. internal laser trimmed resistor networks establish the in-amp and difference amplifier gains (66 v/v and 0.4 v/v, respectively), and stabilize the AD8452 performance across the rated operating temperature range. desired battery cycling current and voltage levels are established by applying precise control voltages to the iset and vset inputs. actual charge and discharge current levels are sensed (usually by a high power, highly accurate shunt resistor) whose value is carefully selected according to system parameters. switching between constant current (cc) and constant voltage (cv) loop integration is instantaneous, automatic, and completely transparent to the observer. a logic high at the mode input selects the charge or discharge mode (high for charge, low for discharge). the AD8452 simplifies designs by providing excellent performance, functionality, and overall reliability in a space saving 48-lead, 7 mm 7 mm 1.4 mm lqfp package rated for operation at temperatures from ?40c to +85c. functional block diagram ibat in-amp vbat diff amp ismea iset bvmea fault isvn isvp bvn bvp vint 1 mode AD8452 ive0/ive1 bvrefh/ bvrefl isrefh/ isrefl vref vref 0.4 66 cv filter amplifier system control vset vve0/vve1 sync vin dt dh dl scfg dmax freq dgnd cln clp en +dcbus vcl vcl isv bv isv bv ss clvt pwm loop comp (4) mode select cc filter amplifier mosfet driver 16187-001 figure 1.
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AD8452 data sheet rev. 0 | page 2 of 34 table of contents features .............................................................................................. 1 ? applications ....................................................................................... 1 ? general description ......................................................................... 1 ? functional block diagram .............................................................. 1 ? revision history ............................................................................... 2 ? specifications ..................................................................................... 3 ? analog front-end and controller specifications .................... 3 ? pulse-width modulator specifications ..................................... 5 ? digital interface specifications ................................................... 6 ? power supply ................................................................................. 7 ? temperature range specifications ............................................. 7 ? absolute maximum ratings ............................................................ 8 ? thermal resistance ...................................................................... 8 ? esd caution .................................................................................. 8 ? pin configuration and function descriptions ............................. 9 ? typical performance characteristics ........................................... 11 ? in-amp characteristics ............................................................. 11 ? difference amplifier characteristics ....................................... 12 ? cc and cv loop filter amplifiers and vset buffer (except where noted) ............................................................................... 13 ? reference characteristics .......................................................... 15 ? pulse-width modulator ............................................................. 16 ? theory of operation ...................................................................... 18 ? introduction ................................................................................ 18 ? instrumentation amplifier (in-amp) ..................................... 19 ? difference amplifier .................................................................. 20 ? cc and cv loop filter amplifiers .......................................... 20 ? charge and discharge control ................................................. 23 ? input and output supply pins .................................................. 23 ? shutdown ..................................................................................... 24 ? undervoltage lockout (uvlo) ............................................... 24 ? soft start ...................................................................................... 24 ? pwm drive signals .................................................................... 25 ? peak current protection and diode emulation (synchronous) ............................................................................. 25 ? frequency and phase control .................................................. 26 ? maximum duty cycle ............................................................... 26 ? fault input ................................................................................... 27 ? thermal shutdown (tsd) ........................................................ 27 ? applications information .............................................................. 28 ? analog controller ...................................................................... 28 ? functional description .............................................................. 28 ? power supply connections ....................................................... 29 ? current sense in-amp connections ....................................... 29 ? voltage sense differential amplifier connections ................ 29 ? battery current and voltage control inputs (iset and vset) ........................................................................ 29 ? loop filter amplifiers ............................................................... 30 ? selecting charge or discharge options .................................. 30 ? select rcl and r clvt for the peak current limit .................. 30 ? setting the operating frequency and programming the synchonization pin .................................................................... 31 ? programming the maximum duty cycle ............................... 32 ? selecting c ss ................................................................................ 33 ? additional information ............................................................. 33 ? outline dimensions ....................................................................... 34 ? ordering guide .......................................................................... 34 ? revision history 10/2017revision 0: initial version
data sheet AD8452 rev. 0 | page 3 of 34 specifications avc c = 1 5 v, avee = ? 1 5 v , v in = 24 v, and t a = 25c, unless otherwise noted. analog front - end a nd controller specif i cations table 1. parameter test condition s /comments min typ max unit current sense i nstrumenta t ion a mplifier gai n 66 v/v gain error v ismea = 10 v 0.1 % gain drift t a = t min to t max 3 ppm/c offset voltage referred to input (rti) isrefh pin and isrefl pin grounded ?100 +100 v offset voltage drift t a = t min to t max ? 0.6 ? 0.1 + 0.6 v/c input bias current 15 30 na input common - mode voltage range v isvp ? v isvn = 0 v avee + 2.3 avcc ? 2.4 v differential input impedance 150 g? common - mode input impedance 150 g? output voltage swing rl = 10 k? avee + 1.5 avcc ? 1.2 v reference input voltage range isrefh pin and isrefl pin tied together a v ee + 1.5 a v cc ? 1.5 v reference bias current v isvp = v isvn = 0 v 5 a output voltage level shift isrefl pin grounded maximum isrefh pin connected to vref pin 11 12.5 14 mv scale factor v ismea /v isrefh 4.4 5 5.6 mv/v short - circuit current 40 ma common - mode rejection ratio ( cmrr ) v cm = 20 v 120 db temperature coefficient t a = t min to t max 0.01 v/v/c power supply rejection ratio ( psrr ) v s = 1 0 v 1 22 1 4 0 db small signal ?3 db bandwidth 675 khz slew rate v ismea = 10 v 5 v/s voltage sense d ifference amplifier gain 0.4 v/v gain error v in = 10 v 0.1 % gain drift t a = t min to t max 3 ppm/c offset voltage referred to output (rto) bvrefh pin and bvrefl pin grounded ?250 + 250 v offset voltage drift t a = t min to t max ?2 ? 0.1 + 2 v/c differential input voltage range v bvn = 0 v, v bvrefl = 0 v ?17 + 17 v input common - mode voltage range v bvmea = 0 v ?40 + 40 differential input impedance 400 k? input common - mode impedanc e 140 k? output voltage swing rl = 10 k? avee + 1.5 avcc ? 1.2 v reference input voltage range bvrefh pin and bvrefl pin connected avee + 1.5 avcc ? 1.5 v output voltage level shift bvrefl pin grounded maximum bvrefh pin connected to vref pin 11.0 12.5 14.0 mv scale factor v bvmea /v bvrefh 4.4 5 5.6 mv/v short - circuit current 40 ma cmrr v cm = 10 v, rto 9 0 db temperature coefficient t a = t min to t max 0.05 v/v/c psrr v s = 10 v, rto 114 123 db small signal ?3 db bandwidth 3.0 m h z slew rate v bvmea = 10 v 0.9 v/s
AD8452 data sheet rev. 0 | page 4 of 34 parameter test condition s /comments min typ max unit cc and cv loop filter amplifiers offset voltage 150 v offset voltage drift t a = t min to t max ?1 + 0.02 1 v/c input bias current ?5 +5 na input common - mode voltage range avee + 1.5 avcc ? 1.8 v outp ut voltage swing v vint voltage ran ge avee + 1.5 5 v source short - circuit current 1 ma sink short - circuit current 40 ma psrr v s = 10 v 113 122 db small signal gain bandwidth product 3 mhz slew rate v vint = 10 v 1 v/s cc to cv transitio n time 1.8 s vset voltage buffer nominal gain 1 v/v offset voltage 150 v offset voltage drift t a = t min to t max ?1 + 0.06 + 1 v/c input bias current ?5 +5 na input/output voltage range avee + 1.5 avcc ? 1.8 v short - circuit curren t 40 ma psrr v s = 10 v 113 122 db small signal ?3 db bandwidth 4 mhz slew rate v vsetbf = 10 v 1 v/s voltage reference nominal output voltage with respect to agnd 2.5 v output voltage error 1 % temperature drift t a = t min to t m ax 16 ppm/c line regulation v s = 10 v 10 ppm/v load regulation i vref = 1 ma (source only) 3 00 ppm/ma source short - circuit current 15 ma
data sheet AD8452 rev. 0 | page 5 of 34 pulse - width modulator specifications table 2. parameter test con ditions/comments min typ max unit soft start (ss) ss pin current v ss = 0 v 4 5 6 a ss threshold rising switching enable threshold 0.52 0.65 v ss threshold falling switching disable threshold 0.4 0.5 v end of soft start asynchronous to synchron ous threshold 4.4 4.5 4.6 v pwm control f requency frequency range r freq = 33.2 k? to 200 k? 50 300 khz oscillator frequency r freq = 100 k? 90 100 110 khz freq pin voltage r freq = 100 k? 1.1 1.255 1.4 v sync output (internal frequency control) v scfg 4.53 v or scfg pin floating internal sync range for sync output 50 300 khz sync output clock duty cycle v scfg = v vreg , r freq = 100 k? 40 50 60 % sync sink pull d own resistance v scfg = 5 v, i sync = 10 ma 10 20 ? sync input (external frequency control) v scfg < 4.25 v external sync range for sync input clock 50 300 khz sync internal pull - down resistor 0.5 1 1.5 m ? maximum sync pin voltage for ext ernal sync oper ation 5 v sync threshold rising 1.2 1.5 v sync threshold falling 0.7 1.05 v scfg scfg high threshold rising sync set to input 4.53 4.7 v falling sync set to output 4.25 4.47 v scfg low threshold rising programmable phase shift above threshold 0.55 0.65 v falling no phase shift 0.4 0.5 v scfg pin current r freq = 100 k?, v scfg = dgnd 10 11 12 a dmax maximum internal duty cycle v dmax , v ss , and v scfg = 5 v 97 % dmax setting current v dmax = 0 v, r freq = 100 k? 10 11 12 a dmax and scfg current matching 1 10 % dt dt pin current r freq = 100 k?, v dt = dgnd 20 24 a maximum dt programming voltage see figure 28 3.5 v current limit (cl) clvt clvt p i n current minimum clvt pin vo ltage = 50 mv 16 21 27 a clp, cln common - mode range v clp = v cln 0 8 v input resistance 24 30 36 k ? current limit thresho ld offset v clp = v cln , r clvt = 2.49 k? 50 mv clflg open - drain , active low out put max clflg voltage open - drain outp ut 5.5 v cflg pull - down resistance 8 ? current limit r freq = 100 k?, 16 consecutive clock pulses overload time 160 s cool down time 160 s
AD8452 data sheet rev. 0 | page 6 of 34 parameter test con ditions/comments min typ max unit zero crossing detection (zcd) zcd threshold offset ( v clp + v cln )/2 , for common - mode voltage (cmv) = 0 v to 8 v 0 mv vreg low dropout ( ldo ) regulator output voltage v in = 6 v to 60 v, no external load 4.9 5 5.1 v lo ad regulation v in = 6 v, i out = 0 ma to 5 ma 4.9 5 5.1 v pwm drive logic signals (dh/dl) dl drive voltage no load vreg v dh drive voltage no load vreg v dl and dh sink resistance i dl = 10 ma 1.4 2.6 ? dl and dh source resistance i dl = 10 ma 1.4 2.6 ? dl and dh pull - down resistor 0.5 1 1.5 m? thermal shutdown (tsd) tsd threshold rising 150 c falling 125 c 1 the dmax and scfg current matching specification is calculated by taking the absolute value of the difference between the mea sured i scfg and i dmax currents, dividing them by the 11 a typical val ue, and multiplying this result by 100 . dmax and scfg current matching (%) = (i scfg C i dmax /11 a) 100 digital interface specif i cations table 3. parameter test conditions/comments min typ max unit digital interface, mode input mode pin mode threshold rising 1.2 1.4 v m ode threshold falling 0.7 1.0 v m ode switching time 400 ns precision enable logic (en) maximum en pin voltag e 60 v en threshold rising 1.26 1.4 v en threshold falling 1.1 1.2 v en pin current v en = 5 v, internal pull - d own 0. 2 5 2 a fault active low in put maximum fault pin voltage 60 v fault threshold rising 1.2 1.5 v fault threshold falling 0.7 1.0 v fault pin current v fault = 5 v, internal 8.5 m? pull - down resistor 0.5 2 a
data sheet AD8452 rev. 0 | page 7 of 34 power supply table 4. parameter test conditions/comments min typ ma x unit analog power supply operating voltage range avcc 10 36 v avee ? 26 0 v analog supply range avcc ? avee 10 36 v quiescent current avcc 4.7 6.5 ma avee 4.4 6.0 ma pwm power s u pply (vin) vin voltage range 6 60 v vin supply current r freq = 100 k?, v ss = 0 v, sync = o pen c ircuit (oc), fault = l ow, en = h igh 2.2 3.0 ma uvlo threshold rising v in rising 5.75 6 v uvlo threshold falling v in falling 5.1 5.34 v temperature range specifications tab le 5. parameter min typ max unit temperature range for s pecified p erformance ?40 +85 c operational ?55 +125 c
AD8452 data sheet rev. 0 | page 8 of 34 absolute maximum rat ings table 6. parameter rating analog supply voltage (avcc ? av ee) 36 v pwm supply voltage (vin C dgnd) ?0.3 v to + 61 v internal regulator voltage ( vreg ? dgnd ) 5.5 v voltage input pin s ( isvp, isvn, bvp , and bvn ) avee + 40 v analog controller and front - end pins (isrefh, isrefl, bvrefl, bvrefh, vref, vset, vvp0, bvmea, vve0, vve1, vint, ive0, ive1, ismea, iset) av cc ? 40 v pwm pins sync , mode ? 0.3 v to + 5.5 v dh, dl, ss, dmax, scfg, dt, freq, clvt ? 0.3 v to vreg + 0.3 v current limit sense pins (clp, cln) ?0.3 v to +61 v fault pin and en p in ? 0.3 v to + 61 v maximum digital supply voltage positive analog supply (vreg ? avcc) 0.3 v negative analog supply (vreg ? avee) ?0.3 v maximum digital ground positive analog supply (dgnd ? avcc) 0.3 v negative analog supply (dgnd ? avee) 0.3 v maximum analog ground positive analog supply (agnd avcc) 0.3 v negative analog supply (agnd avee) 0.3 v analog ground with respect to the digital ground (agnd dgnd) maximum 0.3 v minimum 0.3 v storage temperature range 65c to +150c stresses at or above those listed under absolute maximum ratings may cause permanent damage to the product. this is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. operation beyond the maximum operating conditions for extended periods may affect product reliability. thermal resistance thermal performance is directly linked to printed circuit board ( pcb ) design and operati ng environment. careful attention to pcb thermal design is required. table 7 . thermal resistance package type ja 2 unit st -48 1 81 c/w 1 dissipation 0.3, ta = 25c . 2 ja is the natural convection junction to ambient thermal re sistance measured in a one cubic foot sealed enclosure. esd caution
data sheet AD8452 rev. 0 | page 9 of 34 pin configuration an d function descripti ons 4 8 4 7 4 6 4 5 4 4 4 3 4 2 4 1 4 0 3 9 3 8 3 7 3 5 3 4 3 3 3 0 3 1 3 2 3 6 vref 2 9 2 8 2 7 2 5 2 6 2 3 4 7 6 5 1 8 9 1 0 1 2 1 1 isrefh 1 3 freq 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 2 2 2 3 2 4 AD8452 top view (not to scale) avee agnd avcc iset ismea ive0 ive1 vint avcc cln clp clvt dmax ss dt dgnd dh dl vin vreg scfg sync clflg isrefl isrefls isvp isvn bvp bvps bvn bvns bvrefl bvrefls bvrefh vset vvp0 bvmea vsetb vve0 vve1 vint avee mode en fault 16187-002 figure 2 . pin configuration table 8 . pin function descriptions pin no. mnemonic type 1 description 1 isrefh input reference input for the current sense amplifier. c onnect this pin to the vref pin t o shift the current - sense instrumentation amplifier output by 12.5 mv . otherwise, connect this pin to the isrefl pin. 2 isrefl in put reference input for the current sense amplifier. the default connection is to ground. 3 isrefls test kelvin sense pin for the isrefl pin. 4 isvp input current sense instrumentation amplifier positive (noninverting) input. connect this pin to the high side of the current sense shunt. 5 isvn input current sense instrumentation amplifier negative (inverting) inputs. connect this pin to the low side of the current sense shunt. 6 bvp input battery voltage difference amplifier positive (noninverting) inpu t. 7 bvps test kelvin sense pin for the battery voltage differe nce amplifier input , b v p. 8 bvn input battery voltage difference amplifier negative (inverting) input. 9 bvn s test kelvin sense pin for the battery voltage difference amplifier input , bvn . 10 bvrefl input reference input for the voltage sense difference amplifier. the default connection for this pin is to ground. 11 bvrefls test kelvin sense pin for the bvrefl pin. 12 bvrefh input reference input for the difference amplifier. c onnect to t he vref pin t o level sh ift v bvmea by approximately 12.5 mv. otherwise, connect this pin to the bvrefl pin . 13, 21 avee n/a analog negative supply pins. 14 vset input scaled cv loop control input for battery charge or discharge cycle . 15 vvp0 input noni n verting cv loop filter amplifier input for discharge mode. 16 bvmea output scaled battery voltage , difference amplifier output. 17 vsetb output buffered vset voltag e. 18 vve0 input i nverting input of the cv loop filter amplifier when in discharge mode. 19 vve1 input inverting input of the cv loop filter amplifier when in charge mode . 20, 41 vint output aggregated result of the battery voltage and current sense integrat ion . 22 mode logic input logic level input to select between charge and discharge m ode s . bring this pin low for discharge mode, and bring this pin high for charge mode . 23 en logic input log ic level e nable input. drive en logic low to shut down the device. drive en logic high to turn on the device. 24 fault logic in pu t external fault com parator connection . when not connected, this pin is pulled up using a 10 k? resistor to the vreg pin . the dh and dl drivers are disabled w hen fault is l ow, and are e nabled w hen fault is h i gh.
AD8452 data sheet rev. 0 | page 10 of 34 pin no. mnemonic type 1 description 25 clflg output current - limit flag . clflg g oes low and stays low w hen the AD8452 is in current limit mode . connect a 10 k? (minimum ) resistor to the vreg pin. 26 sync input / output c lock synchronization pin. synchronizes the clock ( switching frequency) when mul tiple channels a re phase interleaved . connect a 10 k? (minimum ) resistor to the vreg pin . 27 scfg input / output synchronization configuration pin . see table 10 . 28 vreg output internal ldo 5 v regulator output and internal bias supply. connect a bypass capacit or of 1 f or greater from this pin to ground. 29 vin input supply voltage to the pwm section . vin is typically the same as the output switch s upply voltage. 30 dl output logic drive output for the external low - side metal - oxide semiconductor field - effect transistor (mosfet) driver. 31 dh output logic drive output for the external high - side mosfet driver. 32 dgnd n/a digital and pwm ground. 33 dt output dead time programming pin. connect an external resistor between this pin and ground to set the dead time. do not leave this pin floating . 34 ss output soft start control pin. a capacitor connected from the ss pin to ground sets the soft start ramp time. see the selecting c ss sectio n. 35 dmax input maximum duty cycle input. connect an external resistor to ground to set the maximum duty cycle. if the 97% internal maximum duty cycle is sufficient for the application, tie this pin to vreg. if dmax is left floating, this pin is internal ly pulled up to vreg. 36 freq n/a frequency set pin. connect an external resistor between this pin and ground to set the frequency between 50 khz and 300 khz. when the AD8452 is synchronized to an external clock (slave mode) , set the slave frequency to 90 % of the master frequency by multiplying the master r freq value by 1.11 . 37 clvt input current - limit voltage threshold . with user selected resistor value , clvt establish es a threshold voltage for the current limit comparator. see the select r cl and r clvt for the peak current limit section. 38 clp input current - limit/diode emulation amplifier positive sense pin. 39 cln input current - limit /diode emulation amplifier negative sense pin . 40, 46 avcc n/a analog positive supply pins. 42 ive1 input inverting input of the c c loop filter amplifier when in charge mode . 43 ive0 input inverting input of the c c loop filter amplifier when in discharge mode. 44 ismea output current sense instrumentation amplifier output. 45 iset input scaled cc voltage loop control input for battery charge or discharge cycle s . iset is typically the same for charge and discharge cycle . 47 agnd n/a analog ground. 48 vref output 2.5 v reference . bypass this pin with a high quality 10 nf np 0 ce ramic capacitor in series with a 10 ? ( max imum) resistor . 1 n/a means not applicable.
data sheet AD8452 rev. 0 | page 11 of 34 typical performance characteristics avcc = 15 v, avee = ?15 v, vin = 24 v, t a = 25c, and r l = , unless otherwise noted. in-amp characteristics gain error (ppm) temperature (c) 30 40 50 60 70 80 90 020 ? 10 10 ? 20 ? 30 ? 40 ?100 0 ?20 ?40 ?60 ?80 20 40 60 16187-003 figure 3. gain error vs. temperature input bias current (na) input common-mode voltage (v) 05 ? 10 10 15 ? 5 ? 15 17.0 16.5 16.0 15.5 15.0 14.5 14.0 16187-004 figure 4. input bias current vs. input common-mode voltage input bias current (na) temperature (c) 30 40 50 60 70 80 90 020 ?10 10 ?20 ?30 ?40 16187-005 16 15 14 13 12 17 18 19 isvp isvn figure 5. input bias current vs. temperature ? 60 ?140 10 100k cmrr (db) frequency (hz) ?90 ?110 ?80 ?100 ?120 ?70 ?130 1k 100 10k 16187-006 figure 6. cmrr vs. frequency ? 50 ?160 10 100 1k 10k 100k psrr (db) frequency (hz) ?90 ?110 ?80 ?100 ?120 ?70 ?60 ?130 ?150 ?140 +psrr ?psrr 16187-007 figure 7. psrr vs. frequency 40 30 20 10 0 100 1k 10k 100k 1m 10m gain (db) frequency (hz) 16187-008 figure 8. gain vs. frequency
AD8452 data sheet rev. 0 | page 12 of 34 difference amplifier characteristics gain error (ppm) temper a ture (c) 30 40 50 60 70 80 90 0 20 ?10 10 ?20 ?30 ?40 16187-009 ?260 ?180 ?200 ?220 ?240 ?160 ?120 ?140 isvp isvn figure 9 . gain error vs. temperature ?50 ?130 10 100 1k 10k 100k cmrr (db) frequency (hz) ? 90 ? 110 ? 80 ? 100 ? 120 ? 70 ? 60 16187-010 figure 10 . cmrr vs. frequency ?10 ?140 psrr (db) 10 100 1k 10k 100k frequency (hz) 90 ?110 ?80 ?100 ?120 ?70 ?50 ?60 ?130 ?30 ?40 ?20 +psrr ?psrr 16187-0 1 1 figure 11 . psrr vs. frequency 0 ?10 ?20 ?30 ?40 100 1k 10k 100k 1m 10m gain (db) frequency (hz) 16187-012 figure 12 . gain vs. frequency
data sheet AD8452 rev. 0 | page 13 of 34 cc and cv loop filter amplifiers an d vset buffer (except where noted) input offset voltage (v) input common-mode voltage (v) 05 ?10 10 ?5 ?15 15 150 100 50 0 ?50 ?100 ?150 16187-013 figure 13. input offset voltage vs. input common-mode voltage input bias current (na) temperature (c) 30 40 50 60 70 80 90 020 ?10 10 ?20 ?30 ?40 16187-014 0.15 0.10 0.05 0 ?0.05 0.20 0.25 0.30 figure 14. input bias current vs. temperature input bias current (pa) input common-mode voltage (v) 05 ?10 10 ?5 ?15 15 400 200 0 ?200 ?400 ?600 ?800 ?1000 16187-015 figure 15. input bias current vs. input common-mode voltage ?40 ?30 ?20 ?10 0 10 20 30 40 50 60 70 80 90 temperature (c) 16187-016 1.6 1.7 output source current (ma) 1.5 1.4 1.3 1.2 1.1 1.0 figure 16. output source current vs. temperature
AD8452 data sheet rev. 0 | page 14 of 34 ?20 ?30 ?40 ?50 ?60 ?80 ?70 ?90 ?100 ?110 ?120 ?130 ?140 ?150 psrr (db) 10 100 1k 10k 100k frequency (hz) +psrr ?psrr 16187-017 figure 17 . p srr vs. frequency 10m 1m 120 ?40 ?20 20 0 60 100 40 80 10 100 1k 10k 100k open loop gain (db) frequency (hz) ?45.0 ?67.5 ?90.0 ?112.5 ?135.0 ?157.5 ?180.0 ?202.5 ?225.0 phase (degrees) phase gain 16187-018 figure 18 . open - loop gain and phase vs. frequency for cc and cv loop amplifiers 1.5 1.0 0.5 0 ?0.5 ?1.0 ?1.5 0 25 50 output voltage (v) time (s) 20 10 15 5 35 30 40 45 iset (v) vint (v) 16187-019 figure 19 . cc to cv transition
data sheet AD8452 rev. 0 | page 15 of 34 reference characteri stics 2.498 2.500 2.496 2.494 2.492 2.490 0 2 3 5 7 8 6 1 4 9 10 output voltage (v) output current?sourcing (ma) t = +85c t = +25c t = ?40c 16187-020 figure 20 . sourcing regulation for three values of temperature 300 250 200 150 100 ?55 ?15 5 45 85 65 ?35 25 105 125 source load regulation (ppm/ma) temperature (c) 16187-021 figure 21 . source load regulation vs. temperature
AD8452 data sheet rev. 0 | page 16 of 34 pulse-width modulator temperature (c) 3020 40 50 60 70 80 90 0 ?10 10 ?20?30?40 5.10 v in = 6v v in = 24v v in = 60v ss pin current (a) 5.08 5.06 5.04 5.02 5.00 4.98 4.96 4.94 4.92 4.90 16187-022 figure 22. ss pin current vs. temperature ch1 5.00v 1m ? 20.0m 1 m ? 20.0m 1m ? 20.0m 1 m ? 20.0m 20s/div ch1 3.1v ch3 5.00v ch2 5.00v ch4 5.00v 1 2 4 16187-023 en dh dl sync b w b w b w b w figure 23. timing, referred to startup (0 v to 5 v at en pin), as observed at three logic output pins when AD8452 is in charge mode 1 2 3 4 16187-024 c ss = 0.1f mode = 5v ch1 5.00v 1m ? 20.0m 1m ? 20.0m 1m ? 20.0m 1m ? 20.0m 20ms/div ch1 2.3v ch3 5.00v ch2 2.00v ch4 5.00v en dh dl ss b w b w b w b w figure 24. soft start ramp timing at ss pin, referred to startup (0 v to 5 v at the en pin) as observed at logic level outputs, dh and dl, when AD8452 is in charge mode 16187-025 1 2 3 4 en ss dh dl c ss = 0.1f mode = 0v ch1 5.00v 1m ? 20.0m 1m ? 20.0m 1m ? 20.0m 1m ? 20.0m 20ms/div ch1 2.3v ch3 5.00v ch2 5.00v ch4 5.00v b w b w b w b w figure 25. shows reversal of dh pin and dl pin timing at startup (0 v to 5 v at en pin) when AD8452 is in discharge mode 210 30 70 110 150 190 50 90 130 170 50 150 100 200 250 300 r freq (master) (k ? ) f set (khz) 16187-026 figure 26. r freq (master) vs. switching frequency (f set ) 0 1.5 3.0 4.5 6.0 7.5 9.0 500 450 400 350 300 250 200 150 100 50 0 r scfg (k ? ) phase delay (s) 16187-027 figure 27. r scfg (calculated) vs. phase time delay (t delay )
data sheet AD8452 rev. 0 | page 17 of 34 16187-028 dead time (ns) 0 75 150 125 50 100 25 175 700 600 400 300 500 200 100 0 r dt (k ? ) figure 28. dt pin resistance (r dt ) vs. dead time (t dead ) v reg (v) input voltage (v) 60 33 51 24 42 15 6 5.000 4.998 4.996 4.994 4.992 4.990 4.988 4.986 4.984 t = ? 40c t = +25c t = +85c 16187-029 figure 29. vreg vs. input voltage (v in ) at various temperatures and no load v en (v) temperature (c) 30 40 50 60 70 80 90 020 ?10 10 ?20 ?30?40 16187-030 1.26 1.25 1.24 1.23 1.22 1.21 1.20 1.19 1.18 v en rising v en falling figure 30. en pin threshold voltage (v en ) vs. temperature quiescent current (ma) input voltage (v) 33 42 15 51 60 24 6 2.30 t = ? 40c t = +25c t = +85c 2.25 2.20 2.15 2.10 2.05 2.00 1.95 16187-031 figure 31. quiescent current vs. input voltage (v in ) at various temperatures, en pin low v in uvlo threshold (v) temperature (c) 30 40 50 60 70 80 90 020 ?10 10 ?20 ?30?40 16187-032 5.9 uvlo threshold rising uvlo threshold falling 5.8 5.7 5.6 5.5 5.4 5.3 5.2 figure 32. input voltage (v in ) uvlo threshold vs. temperature
AD8452 data sheet rev. 0 | page 18 of 34 theory of operation introduction lithium ion (li-ion) batteries require an elaborate and time consuming postproduction process known as forming. battery formation consists of a series of charge/discharge cycles that require precise current and voltage control and monitoring. the AD8452 provides not only the stringent current and voltage accuracy requirements, but also a highly accurate pwm, with logic level dh and dl outputs ready for a half-h bridge configured switch mode power output converterall in a highly compact 7 mm 7 mm package. the analog front end of the AD8452 includes a precision current sense in-amp with gain of 66 0.1% and a precision voltage sense difference amplifier with a gain of 0.4 0.1% for battery voltage. as shown in figure 38, the AD8452 provides constant cc/cv charging technologies, with transparent internal switching between the two. typical systems induce predetermined levels of current into or out of the battery until the voltage reaches a target value. at this point, a set constant voltage is applied across the battery terminals, reducing the charge current until reaching zero. the AD8452 features a complete pwm including on-board user adjustable features such as clock frequency, duty cycle, clock phasing, current limiting, soft start timing, and multichannel synchronization. figure 33 is the block diagram of the AD8452, illustrating the distinct sections of the AD8452, including the in-amp and difference amplifier measurement blocks, loop filter amplifiers, and pwm. figure 34 is a block diagram of the AD8452 integrated within a battery formation and test system. the AD8452 is usable over a wide range of current and voltage applications simply by judicious selection of a current sense shunt, selected according to system requirements. 8 7 6 5 4 3 2 9 12 11 10 isvp vreg = 5v isvn 33 28 27 25 34 avee 1 26 35 38 29 isrefh vref isrefls isrefl ive1 ismea ive0 iset vint agnd cln avcc clp vve1 vint vve0 vvp0 vset cl vsetb avcc 37 bvrefh bvps bvrefl bvp bvns bvrefls en bvme a bvn mode 500 ? 100k ? battery current sense ia g = 66 ss mode_b 31 32 avcc 300 ? 60k ? avee avee 36 dh dl vin clvt scfg fault vreg dt ss freq dgnd sync 1m ? 1m ? ss cl ss 1 80k ? 200k ? ss discharge 8.5m ? 200k ? scfg scfg config detect 30 4v 1 sync sync detect avee avcc battery voltage sense da g = 0.4 17 18 15 16 1413 19 20 21 22 23 24 avee clflg avcc 44 40 42 45 39 43 41 4647 48 dmax dmax vreg dmax d c dc dc mode' clflg clflg sync oscillator vreg uvlo tsd band gap mode_b 5a +/? 79.7k ? 2.5v vref 1m ? current limit and diode emulation vset buffer mode_b cv loop filter amplifier soft start amplifier 1.1ma cc loop filter amplifier vctrl comp i dmax 11a iscfg 11a v bg = 1.252v mode_b drive logic 0.3a 1.64pf 10a 20a 20a v freq = 1.252v 16187-033 figure 33. AD8452 detailed block diagram
data sheet AD8452 rev. 0 | page 19 of 34 battery vctrl current sense shunt isvp isvn bvp bvn mode switches (3) battery current (ibat) avee constant current loop filter amplifier 1 vint buffer vsetb vset iset cd cd cd vint ismea bvmea vve1 vve0 vvp0 AD8452 controller set battery voltage set battery current c = charge d = discharge constant voltage loop filter amplifier ive1 ive0 buck boost pwm select ibat polarity 1.1ma vreg clp cln current limit and diode emulation charge discharge 1 dc to dc power conversion compensation matrix in-amp diff amp 16187-034 figure 34. signal path of a li-ion battery formation and test system using the AD8452 instrumentation amplifier (in-amp) figure 35 is a block diagram of the AD8452 in-amp used to monitor battery current when connected to a low ohmic value shunt. the architecture of the in-amp is the classic 3-op-amp topology, similar to the analog devices, inc., industry-standard ad8221 or ad620 , and is configured for a fixed gain of 66 v/v. this architecture, combined with adi exclusive precision laser trimming, provides the highest achievable cmrr and optimizes error free (gain error better than 0.1%) high-side battery current sensing. for more information about instrumentation amplifiers, see a designer's guide to instrumentation amplifiers . 10k ? 10k ? 20k ? 500 ? instrumentation amplifier g = 66 isvn isvp + current shunt ismea ? current shunt subtractor 100k ? 19.5k ? isrefh isrefl 2.5v vref charge/ discharge polarity inverter 10k ? 10k ? 305 ? optional connection for vos of 12.5mv g = 2 +/? +/? 16187-035 figure 35. simplified block diagram of the precision 3-op-amp in-amp reversing polarity when charging and discharging figure 34 shows that during the charge cycle, the power converter drives current into the battery, generating a positive voltage across the current sense shunt. during the discharge cycle, however, the power converter drain s current from the battery, generating a negative voltage across the shunt resistor. in other words, the battery current reverses polarity when the battery discharges. when in the constant current discharge mode control loop, this reversal of the in-amp output voltage drives the integrator to the negative rail unless the polarity of the target current is reversed. to solve this problem, the AD8452 in-amp includes a double pole, double throw switch preceding its inputs that implements an input polarity inversion, thus correcting the sign of the output voltage (see figure 33). this multiplexer is controlled via the mode pin. when the mode pin is logic high (charge mode), the in-amp gain is noninverting, and when the mode pin is logic low (discharge mode), the in-amp gain is inverting. the polarity control of the current sense voltage to the input of the in-amp enables the integrator output voltage (vint) to always swing positive, regardless of the polarity of the battery current.
AD8452 data sheet rev. 0 | page 20 of 34 in - amp offset option as shown in figure 35 , the in - amp reference node is connected to the isrefl pin and isrefh pin via an internal resistor divider. this resistor divider can be used to i ntroduce a temperature insensitive offset to the output of the in - amp such that it always reads a voltage higher than zero for a zero differential input. because the output voltage of the in - amp is always positive, a unipolar analog - to - digital converter (a dc) can digitize it. when the isrefh pin is tied to the vref pin with the isrefl pin grounded, the voltage at the ismea pin is increased by an offset voltage, v os , of 1 2 .5 mv , guaranteeing that the output of the in - amp is always positive for zero different ial inputs. other voltage shifts can be realized by tying the isrefh pin to an external voltage source. the gain from the isrefh pin to the ismea pin is 5 mv/v. for zero offset, connect the isrefl pin and isrefh pin to ground. battery reversal and overvolt age protection the AD8452 in - amp can be configured for high - side or low - side current sensing. if the in - amp is configured for high - side current sensing (see fig ure 34 ) and the battery is connected backward, the in - amp inputs may b e held at a voltage that is below the negative power rail (avee), depending on the battery voltage. to prevent damage to the in - amp under these conditions, the in - amp inputs include overvoltage protection circuitry that allows them to be held at voltages o f up to 55 v from the opposite power rail. in other words, the safe voltage span for the in - amp inputs extends from avcc ? 55 v to avee + 55 v. difference amplifier figure 36 is a block diagram of the difference amplifier used to monitor the battery voltage. the architecture of the difference amplifier is a subtractor amplifier with a fixed gain of 0.4 v/ v . t his gain value allows the difference amplifier to funnel the voltage of a 5 v battery to a level that can be read by a 5 v adc with a 4.096 v reference. bvrefl bvp bvn 200k 200k 80k 79.7k AD8452 diffamp bvrefh vref bvmea 300 60k connect for vos of 12.5mv + battery terminal ? battery terminal 16187-036 figure 36 . difference am plifier simplified block diagram the resistors that form the difference amplifier gain network are laser trimmed to a matching level better than 0.1%. this level of matching minimizes the gain error and gain error drift of the difference amplifier while m aximizing the cmrr of the difference amplifier . this matching also allows the controller to set a stable target voltage for the battery over temperature while rejecting the ground bounce in the battery negative terminal. like the in - amp , the difference amp lifier can also level shift its output voltage via an in ternal resistor divider that is tied to the difference amplifier reference node. this resistor divider is connected to th e bvrefh pin and bvrefl pin. when the bvrefh pin is tied to the vref pin with t he bvrefl pin grounded, the voltage at the bvmea pin is increased by 12.5 mv , guaranteeing that the output of the difference amplifier is always positive for zero differential inputs. other voltage off s e ts are realized by tying the bvrefh pin to an externa l voltage source. the gain from the bvrefh pin to the bvmea pin is 5 mv/v. for zero offset, tie the bvrefl pin and the bvrefh pin to ground. cc and cv loop filte r amplifiers the cc and cv loop filter amplifiers are high precision, low noise specialty ampli fiers with very low offset voltage and very low input bias current. these amplifiers serve two purposes: ? using external components, the amplifiers implement active loop filters that set the dynamics (transfer function) of the cc and cv loops. ? the amplifier s perform a seamless transition from cc to cv mode after the battery reaches its target voltage. figure 37 is a functional block diagram of the AD8452 cc and cv feedback loops for charge mode ( the mode pin is logic high). for illu strati ve purposes, the external networks connected to the loop amplifiers are simple rc networks configured to form single - pole inverting integrators. this type of configuration exhibits ve ry high dc precision when the feedback loop is closed , due to the h igh loop gain when the feedback loop is in place . the outputs of the cc and cv loop filter amplifiers are internally connected to the vint pins via an analog nor circuit (minimum output selector circuit), such that they can only pull the vint node down. in other words, the loop amplifier that requires the lowest voltage at the vint pins is in control of the node. thus, only one loop, cc or cv, can be in control of the system charging control loop at any given time. when the loop is inactive (open, such as w hen the en pin is low) , the voltage at the vint pins must be railed at avcc.
data sheet AD8452 rev. 0 | page 21 of 34 iset cc loop amplifier cv loop amplifier ive1 isvn bvp bvn ismea bvmea ia da vvset vset r1 viset mode vint vint isvp min output select vve1 r2 vset buffer vsetb 5v ? + ? + ? + ? + 66 0.4 c2 c1 i bat shunt r s bat gh ? bridge and lpf gl i ac ? bridge driver dh dl pwm dh dl hvac/12v dc inverter/converter vctrl/ comp 1 16187-037 figure 37 . functional block diagram of the cc and cv loops in charge mode (mode pin high) the viset voltage source and vvset voltage source set the ta rget constant current and the target constant voltage, respectively. when the cc and cv feedback loops are in a steady state, the charging current is set at i bat = s ia iset r g v i bat is the steady state charging current. g ia is the in - amp g ain . r s is the value of the shunt resistor. the target voltage is set at v bat = da vset g v here v bat is the steady state battery voltage. g da is the difference amplifier gain. because the offset voltage of the loop amplifiers is in series wit h the target voltage sources, v iset and v vset , the high precision of these amplifiers minimizes this source of error. charging lithium - ion (li - ion) cell s c harging li - i on cells is a demonstrably more difficult process than charging most other batteries empl oying recyclable technologies. the v oltage margin of error between optimum storage capacity and damage caused by overcharge is around 1% . thus, li - ion cells are more critical to over /under charging than any other type battery style, rechargeable or not . li - ion batteries also exhibit the highest energy density per unit of weight and volume than any other style . such h igh levels of energy density ma k e them the first choice f or portable applications , large and small, from cell phone s to high capacity energy sto rage banks. r ealiz ing their greatest potential requires careful attention to their charge characterization signature. c oncepts of constant current (cc) and constant voltage (cv) batteries can be charged in constant current or constant voltage modes . figure 38 shows a typical cc/cv multiphase charg e profile for a li - ion battery. in the first stage of the charging process, the battery is charged with a cc of 1 a. when the battery voltage reaches a target voltage of 4.2 v, the charging process transitions such that the battery is charged with a cv of 4.2 v. 1.25 0 0.25 0.50 0.75 1.00 0 1 2 3 4 5 battery current (a) time (hours) 5 4 3 2 1 battery voltage (v) current (a) voltage (v) 1a cc charge begins transition from 1a cc to 4.2v cv voltage rises to vset voltage rises to vset charge terminates 16187-038 figure 38 . representative li - ion battery charge profile showing seamless cc to cv transition the following sequence of events describ e s how the AD8452 implements a typical cc/cv charging profile required for a li - ion battery . the scenario assumes a newly manufactured , unformed, never before charged battery , and the c harge and discharge voltage and current levels along with appropriate t ime intervals have alread y been established empirically. energy levels (cc, cv , and time intervals are just a small percent of the battery final ratings). for this example, assume a 3.2 v 10 ah battery is charging at ibat = 2 a and vbat = 4.2 v. the proces s begins with i set = 66 mv and v set = 1.68 v , configured for charge mode. following the target vset and iset , t he system is enabled by applying a logic high to the en pin .
AD8452 data sheet rev. 0 | page 22 of 34 1. at turn on, the default start - up voltages at the ismea pin and bvmea pin are both ze ro , and both integrators (loop amplifiers ) begin to ramp, increasing the voltage at the vint node. ( t he voltage at the vint pin always rise s following an enable regardless of mode setting). 2. as the voltage at the vint node increases, the output current i bat from the power converter starts to rise. 3. when the i bat current reaches the target cc steady state value i bat , the battery voltage is considerably less than the target steady state value, v bat . therefore, the cv loop amplifier forces its output voltage hig h enough to disconnect itself from vint. t he cc loop prevails, maintaining the target charge current until the target vbat is achieved and the cc loop stops integrating. 4. due to the analog or circuit , the loop amplifiers can only pull the vint node down . t h e cc loop takes control of the charging feedback loop, and the cv loop is disabled. 5. as the charging process continues, the battery voltage increases until it reaches the steady state value, v bat , and the voltage at the bvmea pin reaches the target voltage, v vset . 6. the cv loop tries to pull the vint node down to reduce the charging current (i bat ) and prevent the battery voltage from rising any further. at the same time, the cc loop tries to keep the vint node at its current voltage to keep the battery current at i bat . 7. because the loop amplifiers can only pull the vint node down due to the analog nor circuit, the cv loop takes control of the charging feedback loop, and the cc loop is disabled. the analog or (minimum output selector) circuit that couples the out puts of the loop amplifiers is optimized to minimize the transition time from cc to cv control. any delay in the transition causes the cc loop to remain in control of the charge feedback loop after the battery voltage reaches its target value. therefore, t he battery voltage continues to rise beyond v bat until the control loop transitions; that is, the battery voltage overshoots its target voltage. when the cv loop takes control of the charge feedback loop, it reduces the battery voltage to the target voltag e. a large overshoot in the battery voltage due to transition delays can damage the battery; thus, it is crucial to minimize delays by implementing a fast cc to cv transition. figure 39 is the functional block diagram of the ad845 2 cc and cv feedback loops for discharge mode (mode logic pin is low). in discharge mode, the feedback loops operate in a similar manner as in charge mode. the only difference is in the cv loop amplifier, which operates as a noninverting integrator in disc harge mode. for illustration purposes, the external networks connected to the loop amplifiers are simple rc networks configured to form single - pole integrators . iset cc loop amplifier cv loop amplifier ive0 ismea bvmea ia da vvset r2 vset r1 mode vint r s vint gh half bridge and lpf min output select vve0 vvp0 r2 c2 vset buffer vsetb 1 5v ? + ? + ? + ? + 66 0.4 gl ac i ac half bridge driver dh dl pwm dh dl inverter 12v dc bat ? + viset shunt i bat isvn bvp isvp bvn 16187-039 figure 39 . functional block diagram of the cc and cv loops in disc harge mode (mode pin low)
data sheet AD8452 rev. 0 | page 23 of 34 compensation in battery formation and test systems, the cc and cv feedback loops have significantly different open - loop gain and crossover frequencies; therefore, each loop requires its own frequency compensation. th e active filter architecture of the AD8452 cc and cv loops allows the frequency response of each loop to be set independently via external components. moreover, due to the internal switches in the cc and cv amplifiers, the frequency response of the loops i n charge mode does not affect the frequency response of the loops in discharge mode. unlike simpler controllers that use passive networks to ground for frequency compensation, the AD8452 allows the use of feedback networks for its cc and cv loop filter amp lifiers. these networks enable the implementation of both proportional differentiator (pd) type ii and proportional integrator differentiator (pid ) type iii compensators. note that in charge mode, both the cc and cv loops implement inverting compensators, whereas in discharge mode, the cc loop implements an inverting compensator, and the cv loop implements a noninverting compensator. as a result, the cv loop in discharge mode includes an additional amplifier, the vset buffer , to buffer the vset node from th e feedback network vint b uffer . charge and discharge control conditions t o charge and discharge a battery battery charging and discharging requires separate paradigms in terms of the analog requirements and the pwm configurations. these paradigms are based on manufacturer provided inf ormation , most importantly the c rating where c is simply the battery capacity expressed in a mpere hours. f or example, if the battery is c rated as 10 ah , and the charge rate is specified as 0.2 c, the charge current is 2 a for a duration of 5 hours. to charge, the applied voltage must be greater than the voltage of the battery under charge and the current must not exceed the manufacturers specification, usually expressed as a fraction of the full c rating. when discharging, the opposite conditions apply ; the discharge voltage must be less than the unloaded battery voltage , and the current flows out of the battery, reversing the polarity of the shunt voltage. multiple charge / discharge sequenc es can last for days at a time before the battery achieves its optimum storage capacity , and the charge / discharge currents and voltages must be accurately monitored . mode pin the mode pin is a logic level in put that select s charge with a logic high (v mode > 2 v) or discharge with a logic low ( v mode < 0.8 v) . a ll the analog and pwm circuit ry for charg ing and discharging of the batter y is configure d and is latched in when the en pin goes high . the mode pin controls the polarity of the i nternal analog loop and the dh/dl sequence . in charge mode, d h precedes dl ; in discharge mode, dl precedes dh. when the AD8452 operates in charge mode, the pwm operates in a buck configuration. in discharge mode, the configuration changes to boost. s ee figure 40 and figure 41 for the AD8452 dh and dl behavior in each mode. on the rising edge of en , the state of the mode pin is latched, preventing the mode of operation from being changed while the device is enabled. to change between charge and discha rge modes of operation, shut down or disable the AD8452 , adjust the mode pin to change the operating mode, and r e ena ble the system. the operating mode can be changed when the en pin is driven low, the fault pin is driven low, or the ad845 2 is disabled via a tsd event or uvlo condition. on the rising edge of the fault control signal, the state of the mode pin is latched, preventing the mode of operation from being changed while the device is enabled. 4.5v vreg (5v typ) 0.5v 0v pin dl 2.5v (typ) pin dh internal ramp (4v p-p) vreg (5v typ) dh and dl in charge mode 0v 0v 16187-040 figure 40 . dh and dl output w aveform s for c harge mode 4.5v vreg (5v typ) 0.5v 0v pin dl 2.5v (typ) pin dh internal ramp (4v p-p) vreg (5v typ) dh and dl in discharge mode 0v 0v 16187-041 figure 41 . dh and dl output waveforms for disc harge mode input and output supply pin s the AD8452 has f ive power supply input pins, a pair each of the internally connected avcc pin and avee pin for the analog section and i nput vin for the pwm section . the maximum supply voltage for the vin pin is 60 v; i f operating with an input voltage greater than 50 v, see figure 42 for recommend ed additional input filtering . supply > 50v AD8452 r 4.7f vin c 16187-042 figure 42 . recommended filter configuration for input voltages greater t han 50 v
AD8452 data sheet rev. 0 | page 24 of 34 for optimum protection from switching and other ambient noise, all of these supply pins must be bypassed to ground with high quality ceramic capacitors (x7r or better), located as near as possible to the device. vreg is an internal 5 v supply that powers the control circuitry including all the current sources for user selected pwm features. it is active as long as vin is above the internal uvlo (5.75 v typical). vreg may be used as a pull-up voltage for the mode, sync, dmax, and fault pins and any other external pull-ups as long as the additional current does not exceed 5 ma. bypass the vreg pin to ground with a 1 f ceramic capacitor. shutdown the en input turns the AD8452 pwm section on or off and can operate from voltages up to 60 v. when the en voltage is less than 1.2 v (typical), the pwm shuts down, and dl and dh are driven low. when the pwm shuts down, the vin supply current is 15 a (typical). when the en voltage is greater than 1.26 v (typical), the pwm is enabled. in addition to the en pin, the pwm is disabled via a fault condition flagged by an tsd, an undervoltage lockout (uvlo) condition on vin, or an external fault condition via the fault pin. when changing the operating mode, it is necessary to disable the AD8452 by setting the en pin low. undervoltage lockout (uvlo) the uvlo function prevents the pwm from turning on until voltage v in 5.75 v (typical). the uvlo enable state has ~410 mv of hysteresis to prevent the pwm from turning on and off repeatedly if the supply voltage to the vin pin ramps slowly. the uvlo disables the pwm when v in drops below 5.34 v (typical). soft start the AD8452 has a programmable soft start that prevents output voltage overshoot during startup. when the en pin goes high, an internal 5 a current source connected to the ss pin begins charging the external capacitor, c ss , that is connected to vreg (5 v), creating a linear voltage ramp (v ss ) that controls several time sensitive pwm control functions. when v ss < 0.52 v (typical), the dh and dl logic outputs are both lo w. w hen v ss ex ceeds 0.52 v (typical), nonsynchronous switching i s e nabled, e ither th e dh p in o r th e dl p in l ogic output beco me active, and th e pwm duty c ycle gradually increases. when v ss > 4.5 v (typical), synchronous switching is enabled (see figure 43 and figure 44). 16187-043 4.5v 0.52v 0v en 5v ss synchronous operation enabled at ~90% ramp pwm switching enabled at ~10% ramp begin ramp en goes high 0v 5v dl 5v dh 5v dl follows dh begins figure 43. d h and dl se quence in charge mode dl 5v dh 5 v dl follows dh begins 16187-044 en synchronous operation enabled at ~90% ramp pwm switching enabled at ~10% ramp en goes high 0v 5v 4.5v 0.52v 0v 5v ss begin ramp figure 44. dh and dl sequ ence in discharge mode in conjunction with the mode pin, the vss ramp also establishes when the dh and dl, logic outputs and thus the output fet switches, become active. in charge mode (mode high), the pulse sequence at the dh pin precedes that at the dl pin. conversely, in discharge mode, the sequence is reversed and the dl pin precedes the dh pin. the duty cycle of the dh and dl drive pins increase in proportion to the ramp level, reducing the output voltage overshoot during startup (see the selecting css section).
data sheet AD8452 rev. 0 | page 25 of 34 upper switch gate drive (dh) soft start (pin ss) current limit threshold (v clvt ) repeated current limit violation detected for up to 16 counts cool down pin ss goes low and normal soft start (ss) begins current limit flag (pin clflg) 0v reset current-limit normal soft start sequence i rcl pin dh and pin dl go low for 16 counts 5v 0v t 16187-046 figure 45 . recovery from a peak curren t - limit event pwm drive signals the ad84 52 has two 5 v logic level output drive signals, dh and dl , that are compatible with mosfet drivers s uch as the adu m3223 or adum7223 . th e dh and dl drive signals synchronously turn on and off the high - side and low - side switches driven from the external driver. the AD8452 provides a resistor programmable dead time to prevent the dh pin and dl pin from transitioning at the same time, as show n in figure 46 . connect a resistor from the dt pin to ground to program the dead time. dl dh t dead t dead 16187-045 figure 46 . dead time (t dead ) between dh and dl transitions when driving capacitive loads with the dh and dl pins, a 20 ? resistor must be placed in series with the capacitive load to reduce ground noise and ensure signal integrity. peak current protec tion and diode emulation (s ynchronous ) peak current - limit detection the AD8452 provides an adj ustable peak current limit for fast response to overcurrent conditions. when the peak current limit is reached, the main switching fet is turned off , limiting the peak current for the switching cycle and the clflg pin is driven low. when the peak inductor current exceeds the programmed current limit for more than 16 consecutive clock cycles, a peak current overload condition occurs. if the current overload condition exists for less than 16 consecutive cycles, the counter is reset to zero and the peak curren t overload condition is avoided. during the peak current - limit condition, the ss capacitor is discharged t o ground , and the drive signals ( dl and dh ) are disabled for the next 16 clock cycles to allow the fets to cool down ( current overload mode). when the 16 clock cycles expire, the AD8452 restarts with a new soft start cycle. figure 45 shows the sequence for a peak current - limit event . as shown in figure 47 , the inductor c urrent , i rcl , is sensed by a low value resistor, r cl ( for example, 5 m ) , plac ed between th e output inductor and capacitor . the i rcl current is bidirectional, depending on whether the AD8452 is in charge or discharge mode. t he mode pin automatically controls the polarity of the voltage sampled across r cl to set the peak current - limit detection. becaus e the average output voltage at the junction of the low - pass filter inductor and capacitor is equal to the battery potential , the common - mode voltage is reject ed , leaving only the desired differential result .
AD8452 data sheet rev. 0 | page 26 of 34 peak current limiting and diode emulation vreg (clp ? cln) vreg mode dl dh clvt i clvt = 20a r clvt v 1mv AD8452 duty cycle dh duty cycle dl cur lim sync off cln clp +dcbus vrcl rcl i rcl vbat rsh v clvt 16187-047 + ? figure 47 . peak current limiting and diode emulation block diagram the threshold voltage for the peak current comparator is user adjustable by connecting a resistor from the current - limit voltage threshold ( clv t pin ) to ground . the AD8452 generates this voltage from a 20 a current source (see the select r cl and r clv t for the peak current limit section). diode emulation/ s ynchronous m ode o peration the rcl current sense res istor is also used to detect and control current reversal. when the voltage across r cl drops to ? 5 mv v rcl + 5 mv ( f or charge and discharge modes ) during the synchronous fet switching cycle, the synchronous fet is turned off to st op the flow of reverse current. information on how to set the current limit and the current sense resistor rcl is available in the applications information section. 2.5a 0a dl dh 2.5a p-p dh and dl with inductor current while in charge mode diode emulation begins inductor current 16187-048 figure 48 . diode emulation in charge mode , l ow charge current required frequency and phase control the freq, sync, and scfg pins determine the source, frequency, and synchronization of the clock signal that operates the pwm control of the AD8452 . internal frequency control the AD8452 frequency can b e programmed with an external resistor connected between freq and ground. the frequency range can be set from a minimum of 50 khz to a maximum of 300 khz. if the scfg pin is tied to vreg, forcing v scfg 4.53 v (typical), or if the scfg pin is left floatin g, the sync pin is configured as an output, and the AD8452 operates at the frequency set by r freq , which outputs from the sync pin through the open - drain device. the output clock of the sync pin operates with a 50% (typical) duty cycle. in this config urati on, the sync pin can synchronize other switching regula tors in the system to the AD8452 . when the sync pin is configured as an output, an external pull - up resistor is needed from the sync pin to an external supply. the vreg pin of the AD8452 can be used as the external supply rail for the pull - up resistor. external frequency control when v scfg 0.5 v (typical), the sync pin is configured as an input, the AD8452 synchronizes to the external clock applied to the sync pin, and the AD8452 operates as a slave d evice. this synchronization allows the AD8452 to operate at the same switching frequency with the same phase as other switching regulators or devices in the system. when operating the AD8452 with an external clock, select r freq to provide a frequency that approximates but is not equal to the external clock frequency, which is further explained in the applications information section. operating frequency phase shift when the voltage applied to the scfg pin is 0.65 v < v scfg < 4.25 v , the sync pin is configured as an input, and the AD8452 synchronizes to a phase shifted version of the external clock applied to the sync pin. to adjust the phase shift, place a resistor (r scfg ) from scfg to ground. the phase shift can be used to reduce t he input supply ripple for systems containing multiple switching power supplies. maximum duty cycle referring to figure 52, t he maximum duty cycle of the AD8452 can be externally programmed f o r any value between 0% and 97% by inst alling a resistor fr o m the dmax pin to ground. the maximum duty cycle defaults to 97% if the dmax pin is left float ing or connected to 5 v ( the vreg pin ).
data sheet AD8452 rev. 0 | page 27 of 34 f ault input the AD8452 fault pin is a logic le vel input intended to be driven b y an external fault detector. the external fault signal sto ps pwm operation of the system to avoid damag e to the application and components. when a voltage of less tha n 1.0 v (typical) is applied to the fault pin, the AD8452 is disabled , driving the dl and dh pwm drive signals low . t he soft start capacitor (c ss ) is discharged through a switch until a voltage 1.2 v is applied to the fault pin, and the AD8452 resume s switching. the fault pin sustains volt ages as high as 6 0 v . thermal shutdown (ts d) the AD8452 has a tsd protection circuit. the tsd triggers and disables switching when the junction temperature reaches 150c (typical). while in ts d, the dl and dh signals are driven low, the c ss cap acitor disch arges to ground, and vreg remains high. normal operation resumes w hen the junction tempera ture decreases to 135c (typical) .
AD8452 data sheet rev. 0 | page 28 of 34 applications informa tion analog controller this section describes how to use the AD8452 in the context of a battery formation a nd test system and includes design example s. functional descripti on the AD8452 is a precision analog front end and controller for battery formation and test systems. such systems are differentiated from typical battery charger or battery management systems by the high level of voltage and current measurement precision required to optimize li - ion batteries for capacity and energy density. figure 49 shows the analog signal path of a simplified switching battery format ion and test system using the AD8452 controller . the AD8452 is suitable for systems that test and form li - ion and the legacy nicad and nimh electrolyte batteries . the output is a digital format (pwm), designed to drive a switching power output stage. the a d8452 includes the following blocks (see figure 33 a nd the theory of operation section for more information): ? a fixed gain in - amp that senses low - side or high - side battery current. ? a fixed gain difference amplifier that measures the terminal voltage of the battery. ? two loop filter error amplifiers that receive the battery target current and voltage and establish the dynamics of the cc and cv feedback loops. ? a minimum output selector circuit that combines the outputs of the loop filter error amplifiers to perform automatic cc to cv switching. ? a pwm with high - and low - side half bridge logic l evel output s suitable for driving a mosfet gate driver. ? a 2.5 v reference whose output node is the vref pin. ? a logic input pin (mode) that switches the controller configuration between charge mode ( high ) and discharge mode ( low ) . battery vctrl current sense shunt clp cln bvp bvn mode switches (3) battery current (ibat) avee constant current loop filter amplifier 1 vint buffer vsetb vset iset c d c d c d vint ismea bvmea vve1 vve0 vvp0 AD8452 controller set battery voltage set battery current compensation matrix c = charge d = discharge constant voltage loop filter amplifier ive1 ive0 c d d d c d d d c c avcc dc to dc power conversion buck boost pwm level shifter select ibat polarity 1.1ma vreg isvp isvn output switches lpf current limit and diode emulation rcl 1 pgda pgia 16187-049 figure 49 . complete signal path of a battery test or formation system suitable for l i - ion batteries
data sheet AD8452 rev. 0 | page 29 of 34 power supply connect ions the AD8452 requires t hree analog power supplies (avcc , vin , and avee) . two separate gr ound pins , agnd and dgnd , provide option s for isolating analog and digital ground paths in high nois e environments . in most applications , however, these two pins can be connec ted to a common ground. avc c and ave e power all the analog block s, including the in - amp , difference amplifier , and op amps . vin powers a n internal 5 v ldo regulated supply (vreg) that powers the mode log ic and pwm . the rated absolute maximum value for avcc ? avee is 36 v, and the minimum operating avcc and avee voltages are + 10 v and ? 26 v, respectively. due to the high psr r of the AD8452 analog circuitry , the avc c pin can be connected directly to the high current po wer bus (the input voltage of the power converter) without risking injection of supply noise to the controller outputs. a commonly used power supply combination is +1 2 v for avc c and ? 5 v for avee . the 1 2 v rail for avcc provides enough headroom to the in - amp such that it can be connected in a high - side curre nt sensing configuration. the ? 5 v avee rail allows the difference amplifier output to become negative if the battery under test (but) is accidental ly connected in reverse. the condition can be detected by monitoring bvmea for reverse voltage. it is good practice to connect decoupling capacitors to all the supply pins. a 1 f ceramic capacitor in parallel with a 0.1 f capacitor is recommended. current sense in- amp connections for a description of the i n strumentation a mpli fier, see the theory of operation section, figure 33, and figure 35 . the in - amp fixed gain i s 6 6 v/v . current sensors two comm on options for current sensors are isolated current sensing transducers and shunt resistors. isolated current sensing transducers are galvanically isolated from the power converter and are affected less by the high frequency noise generated by switch mode power supplies. shunt resistors are far less expensive, easier to deploy and generally more popular . if a shunt resistor sensor is used, a 4 - terminal, low resistance shunt resistor is recommended. two of the four terminals conduct the battery current, wher eas the other two terminals conduct virtually no current. the terminals that conduct no current are sense terminals that are used to measure the voltage drop across the resistor (and, therefore, the current flowing through it) using an amplifier such as th e in - amp of the AD8452 . to interface the in - amp with the current sensor, connect the sense terminals of the sensor to the isvp pin and isvn pin of the AD8452 (see figure 50). optional low - pass filter due to the extremely high impedance of the instrumentation amplifier used for a current shunt amplifier, power stage switching noise can become an issue if the input circuitry is in close proximity to the power stage components. this issue is mitigated by shielding t he input leads with ground potential shielding designed into the pcb artwork and keeping the input leads close together between the current sense shunt and the input pins. connecting an external differential low - pass filter between the current sensor and t he in - amp inputs is also an effective method to reduce the injection of switching noise into the in - amp (see figure 50). isvp 10k 10k 20k 20k 4-terminal shunt i bat battery unter test isvn 10k 10k 305 imeas + ? opt lpf 16187-050 figure 50 . 4 - terminal shunt resistor connected to the current sens e in- amp voltage sense d ifferential a mplifier connections for a description of the difference amplifier , see the theory of operation section, figure 33, and figure 36 . the gain of the difference amplifier is fixed at 0.4 . for AD8452 applications in large installations, the best practice is to connect each battery with a dedicated pair of conductors to avoid accuracy issues. this recommendation app lies whether using wiring harnesses or a distributed pcb approach (mother/ daughter boards) to the system design. battery current and voltage control inputs (iset and vse t) the voltages at the iset pin and the vset pin set the target battery current and vo ltage ( cc mode and cv mode ) and require highly accurate and stable voltage s to drive them . for a locally controlled system, a low noise ldo regulator such as the adp7102ardz - 5.0 is appropriate. f or l arg e scale computer controlled systems, a digital - to - a nalog converter ( dac ) such as the dual channel , 16- bit ad5689rbruz is suitable for these purposes. in either event, the source output voltage and the in - amp and difference amplifier reference pins (isrefh/isrefl and bvrefh/bvrefl , respectively ) must use the same ground reference . for example, if the in - amp reference pins are connected to agnd, the voltage source connected to iset must also be refere nced to agnd. in the same way, if the difference amplifier
AD8452 data sheet rev. 0 | page 30 of 34 reference pins are connected to agnd, the voltage source connected to vset must also be referenced to agnd. in constant current mode, when the cc feedback loop is in a steady state, the iset input sets the battery current as follows: i bat = s ia iset r g v s iset r v 66 where: g ia is the in - amp gain. r s is the value of the current sense resistor. note that the system accuracy is highly dependent on the physica l properties of the shu nt as well as the in - amp g ia and v iset values . when selecting a shunt, be sure to consider temperature performance as well as basic precision. in constant voltage mode, when the cv feedback loop is in a steady state, the vset input sets the battery voltage a ccording to the equation: v bat = da vset g v 4 . 0 vset v here g da is the difference amplifier gain. therefore, the accuracy and temperature stability of the formation and test system are not only dependent on the accuracy and sta bility of the AD8452 but also on the accuracy external components . loop filter amplifie rs the AD8452 has two loop filter amplifiers, also known as error amplifiers (see figure 49 ). one amplifier is for constant cur rent control (cc loop filter amplifier), and the other amplifier is for constant voltage control (cv loop filter amplifier). the outputs of these amplifiers are combined using a minimum output selector circuit to perform automatic cc to cv switching. table 9 lists the inputs of the loop filter amplifiers for charge mode and discharge mode. table 9 . integrator input connections feedback loop function reference input feedback terminal control the current while discharging a battery iset ive0 control the current while charging a battery iset ive1 control the voltage while discharging a battery vset vve0 control the voltage while charging a battery vset vve1 the cc and cv amplifiers in char ge mode and the cc amplifier in discharge mode are inverting integrators, whereas the cv amplifier in discharge mode is a noninverting integrator. therefore, the cv amplifier in discharge mode uses an extra amplifier, the vset buffer, to buffer the vset input pin (see figure 33 ). in addition, the cv amplifier in discharge mode uses the vvp0 pin to couple the signal from the bvmea pin to the integrator. selecting charge or discharge options to operate t he AD8452 in discharge mode ( including energy recycl ing ) mode, apply a voltage less than 1.05 v (typ ical ) to the mode pin. to operate the AD8452 in charge mode, drive the mode pin high, greater than 1.20 v (typ ical ). the state of the mode pin can change wh en the AD8452 is shut down via the en pin or via an external fault condition signaled on the fault pin, a tsd event, or an uvlo condition. select r cl and r clvt f or the peak current limit figure 47 is the block diagram for peak current limit and diode emulation . note that the current - limit sense resistor is floating between the output filter inductor and capacitor. the current generated by a fault condition defines the peak current. in turn, the pea k current equals the sum of the average current ( rated battery charging or discharging current) and the peak incremental inductor current: i pk = i avg + i max w here : i avg is the b attery charge/discharge current . i lmax is the the inductor saturation current . typically, the peak current level is set to the sum of the average current and the value of the inductor saturation current. use the following equation t o calculate the minimum current - limit sense resistor value : r c l min ( ? ) = ) ( mv 50 a i pk (2) here i pk is the desired peak current limit in a. r c l min is the minimum current limit sense resistor value in ?. 50 mv is the minimum ir drop across rcl for sufficient noise immunity during operation. select the next high er standard resistor value for rcl. next, t he value for r clvt is c alculated using the following equation: r clvt ( ? ) = ? ? ? ? ? ? ? ? clvt cl pk i r i ( ) here r c lv t is the current - limit threshold voltage resistor value in . i pk is the desired peak current limit in a. r cl is the current - limit sense resistor value in ?. i c lv t is the clvt pin current (2 1 a typical ) the AD8452 is designed so that the peak current limit is the same in both the buck mode and the boost mode of operation. a 1% or better tolerance for t he r cl and r s resistors is recommended.
data sheet AD8452 rev. 0 | page 31 of 34 sett ing the operating fr equency and programming the s ynchonization p in operating modes of the AD8452 c lock rely on the state of the freq pin and one of three possible voltage options applied to the scfg pin . see table 10 for a summary of synchronization options . when the voltage at the scfg pin exceeds 4.53 v ( or the pin is floating and internally connected to vreg ) , the AD8452 operates at the frequency set by r freq . the sync pin is c onfigu red as an output , displaying a clock signal at the programmed frequency . in this state , the clock voltage at the sync pin can be used as a master clock for synchroniz ed applications. if v scfg is 0.5 v, the sync pin is configured as an input, and the ad845 2 operates as a slave device. as a slave device, the AD8452 synchronizes to the external clock applied to the s ync pin. if the voltage applied to the scfg pin is 0.65 v < v scfg < 4.25 v, and a resistor is connected between scfg and ground, the sync pin is configured as an input, and the AD8452 synchronizes to a phase shifted version of the external clock applied to the sync pin . whether operating the AD8452 as a master or as a slave device, carefully select r freq using the equations in the following section s. select r freq for standalone or master clock whether master or slave, the clock frequency can be selected graphically or by applying e quation 4 . figure 26 shows the relationship between the r freq (master) value and the programme d switching frequency. simply identify the desired clock frequency on a xis f set , and read the corresponding resistor value on a xis r freq (master) . to calculate the r freq (master) value for a desired master clock synchronization frequen cy, use the following equation: ( ) set master freq f r = r freq (master) is the resistor in k to set the frequency for the master device , and f set is the switching frequency in khz. selecting r freq for a slave device to configure the AD8452 as a slave device, drive v sc fg < 4.53 v , and the device operate s at the frequency of an external clock applied to the sync pin. to ensure proper synchronization, select r freq to set the frequency to a value slightly slower than that of the master clock by using the following equation : r freq (slave) = 1.11 r freq (master) (5 ) where r freq (slave) is the resistor value that appropriately scales the frequency for the slave device, 1.11 is the r freq slave to m aster ratio for synchronization and r freq (master) is the resistor value of the master clock applied to the sync pin. the frequency of the slave device is set to a frequency slightly lower than that of the master device to allow the digital synchronization loop of the AD8452 to synchronize to the master clock period. the slave device can synchronize to a master clock frequency running from 2% to 20% higher than the slave clock frequency . setting r freq (slave) to 1.11 larger than r freq (master) runs the synchronization loop in approximately the center of the adjustment range. programmi ng the external clock phase shift if a phase shift is not required for slave devices, connect the scfg pin of each slave device to ground. for devices that require a phase shifted version of the synchronization clock that is applied to the sync pin of the slave devices, connect a resistor (r scfg ) from scfg to ground to program the desired phase shift. to determine the r scfg value for a desired phase shift ( shift ), start by calculating the frequency of the slave clock (f sl av e ). (slave) freq slave r f 4 10 (khz) = = slave slave f t ( ) here t s l av e is the period of the slave clock in s. f s l av e is the frequ ency of the slave clock in khz. next, determine the phase time delay (t delay ) for the desired phase shift ( shift ) using the following equation: ( ) slave slave t t ? = t del ay is the phase time delay in s . shift is the desir ed phase shift. lastly, use the following equation to calculate t delay : r scfg (k?) = 0.45 r freq ( slave ) (k?) + 50 t delay (s) (9 ) where: r scfg is th e corresponding resistor for the desired phase shift in khz. see figure 27 fo r the r scfg vs. t delay graph. when using the phase shift feature, connect a capacitor of 47 pf or greater in parallel with r scfg . alternatively, the scfg pin can be controlled with a voltage source but if an independent voltage source is used , ensure v scfg vreg under all conditions. when the AD8452 is disabled via uvlo , vreg = 0 v, and the voltage source must be adjusted accordingly to ensure v scfg vreg.
AD8452 data sheet rev. 0 | page 32 of 34 table 10. summary of synchronization o ptions of the AD8452 dc control bias applied t o the scfg pin (v) sync pin i nput /o utput s tate and delay op tions master/slave sync i nput/ output delay 0 to 0.50 input no delay slave 0.65 to 4.25 input 0 s to 7.5 s delay (see figure 27 ) s lave 4.53 to 5 output no delay master figure 51 shows the internal voltage ramp of the AD8452 . the voltage ramp is a well controlled 4 v p - p. 4.5v 0.5v 0v 4v p-p 0.03t 0.97t t 16187-051 figure 51 . internal voltage ramp programmi ng the dead time to adjust the dead time on the synchronous dh and dl outputs, connect a resistor (r dt ) from dt to d gnd and bypass with a 47 pf capacitor. select r dt for a given dead time using figure 28 or calcula te r dt using the following equations. to create a single equation for r dt , combine the equations for v dt and r dt . 76 . 3 ) 00 . 10 (ns) ( ) ( ? = = is the dt pin programming voltage. i dt is the 20 a (typical) internal curr ent source. t dead is the desired dead time in ns. r dt is the resistor value in k? for the desired dead time. to calculate r dt for a given t dead , the resulting equation used is 76 . 3 00 . 10 (ns) ) ( ? = ? programming the maxi mum duty cycle the AD8452 is designed with a 97% (typical) maximum internal dut y cycle. by con necting a resistor from dmax to ground, the maximum duty cycle can be programmed at any value from 0% to 97% by using the following equation: ( ) ? = is the programmed maximum duty cycle. v freq = 1.252 v (typ ical). r dmax is the value of the resistance used to program the maximum duty cycle. r freq is the frequency set resistor used in the application. the dmax current source is equivalent to the programmed current of the freq pin: freq freq freq dmax r v i i = = = i freq , the current programmed on the freq pin. 450 0 0 100 r dmax (k?) duty cycle (%) 100 50 200 150 250 300 350 400 60 20 80 40 t a = +25c maximum duty cycle 97% maximum resistor value (approx 400k?) 16187-052 figure 52 . r dmax vs. duty cycle, r freq = 100 k?, v int = 5 v the default maximum duty cycle of the AD8452 is 97% (typical) even i f the value o f r dmax indicates a lar ger per centage . if a 97% internal maximum duty cycle is sufficient for the application, the dmax pin may be pulled to vreg or le ft floating. the c dmax capacitor connected from the dmax pin to the ground plane must be 47 pf or greater.
data sheet AD8452 rev. 0 | page 33 of 34 selecting c ss there are instances where it is useful to adjust the soft start delay to fit specific applications, for example, to accommodate charge or discharge battery characteristics, and the state of charge. the soft start delay is user adjustable by selecting the value of capacitor c ss . when the en pin goes high, and with a capacitor connected to the ss pin, a 5 a current source, i ss , becomes active and begins charging c ss , initiating a timing ramp determined by the following equation: i = c dv/dt in the limit, dv = 5 v and, because the applied current is 5 a, c ss can be calculated for any desired time by transposing the terms of the equation. therefore, c ss = i( dt /d v ) for a 1 sec delay, c ss = 5 e C 6(1/5) or 1 f, a 0.5 sec delay requires 0.5 f, and so on. additional information the following reference materials provide additional insight and practical information that supplement the data sheet material contained herein: ? an-1319 application note , compensator design for a battery charge/discharge unit using the ad8450 or the ad8451. ? AD8452-evalz (ug-1180) , universal evaluation board for the AD8452 . the AD8452-evalz has an embedded AD8452 with reference and test loops and is designed for product evaluation and experimenters. ? AD8452 system demo user guide (ug-1181) , AD8452 battery testing and formation evaluation board . this user guide features plug and play complete on one channel and a working system, including pc control.
AD8452 data sheet rev. 0 | page 34 of 34 outline dimensions compliant t o jedec s t andards ms-026-bbc t o p view (pins down) 1 12 13 25 24 36 37 48 0.27 0.22 0.17 0.50 bsc lead pitch 1.60 max 0.75 0.60 0.45 view a pin 1 0.20 0.09 1.45 1.40 1.35 0.08 coplanarit y view a ro ta ted 90 ccw se a ting plane 7 3.5 0 0.15 0.05 9.20 9.00 sq 8.80 7.20 7.00 sq 6.80 051706- a figure 53 . 4 8 - lead low profile quad flat package [ lqfp ] (st - 48) dimensions shown in millimeters orde ring guide model 1 temperature range package description package option AD8452 astz ? 40c to + 85c 48 - lead low profile quad flat package [lqfp] s t - 48 AD8452 astz - rl ?40c to +85c 48- lead low profile quad flat package [lqfp] st -48 AD8452 - evalz evaluation board 1 z = rohs compliant part. ? 2017 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d16187 - 0 - 10/17(0)

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